1. Field of the Invention
The present invention relates to a surface treatment of a wafer having an SOI (silicon on insulator) structure which is fabricated in accordance with a method in which an ion-implanted wafer is bonded to another wafer and a portion of the ion-implanted wafer is delaminated to thereby obtain an SOI wafer (called a smart-cut method).
2. Description of the Related Art
Conventionally, two methods have gained wide notice as methods of fabricating wafers having an SOI structure. One method is a SIMOX (separation by implanted oxygen) method in which oxygen ions are implanted into a silicon monocrystal at a high concentration, and heat treatment is then performed at a high temperature in order to form an oxide layer. The other method is a bonding method in which two mirror-polished silicon wafers are bonded together without use of adhesive, and one of the wafers is subsequently made very thin.
In the SIMOX method, the thickness of an SOI layer that becomes a device active region can be determined and controlled through adjustment of an acceleration voltage at the time of oxygen ion implantation. Therefore, the SIMOX method has an advantage of enabling easy formation of a thin SOI layer having a high uniformity of thickness (hereinafter referred to as "thickness uniformity"). However, the SIMOX method has many problems in relation to the reliability of a buried oxide layer, the crystallinity of the SOI layer, and necessity of heat treatment at a temperature of 1300.degree. C. or higher.
Meanwhile, in the wafer bonding method, an oxide film is formed on at least one of two mirror-polished silicon monocrystalline wafers, which are bonded together without use of adhesive and then subjected to heat treatment (typically, at 1100-1200.degree. C.) in order to strengthen the bonding; subsequently, one of the wafers is subjected to grinding or wet etching such that the wafer becomes a thin film, the surface of which is then mirror-polished to form an SOI layer. Therefore, the reliability of the buried oxide layer is high, and the crystallinity of the SOI layer is good. However, since the thin film is formed by means of mechanical machining, there are limits to the thickness and thickness uniformity of the resultant SOI layer.
In the wafer bonding method, not only silicon wafers are bonded together, but also a silicon wafer may be bonded directly to an insulator wafer of SiO.sub.2, SiC, Al.sub.2 O.sub.3, etc., in order to form an SOI layer.
Recently, public attention has been drawn to a new method of fabricating an SOI wafer; a so-called smart-cut method in which an ion-implanted wafer is bonded to another wafer and a portion of the ion-implanted wafer is delaminated to thereby obtain an SOI wafer. In this method, an oxide film is formed on the surface of at least one of two silicon wafers; hydrogen ions or rare gas ions are implanted into the surface of one of the two silicon wafers in order to form a fine bubble layer (enclosed layer) within the wafer; the ion-implanted silicon wafer is superposed on the other silicon wafer such that the ion-implanted surface comes into close contact with the surface of the other silicon wafer via the oxide film; heat treatment is performed to delaminate a portion of the ion-implanted wafer while the fine bubble layer is used as a delaminating plane, in order to form a thin film; and heat treatment is further performed to firmly bond the thin film and the other wafer, to thereby obtain an SOI wafer (see Japanese Patent Application Laid-Open (kokai) No. 5-211128). Also, in this method, since the surface formed as a result of delamination (hereinafter referred to as a "delaminated surface") has a mirror-like surface, an SOI wafer whose SOI layer has a high thickness uniformity is obtained with relative ease. In the final step of the above-described method, the delaminated surface is subjected directly to mirror polishing for removing a very small amount of stock (70-110 nm), called touch polishing, so as to reduce surface roughness and to remove a defect layer.
However, when an SOI layer that had not yet been subjected to touch polishing was evaluated in accordance with a four-step Secco-etching disclosed by H. Gassel et al. (J. Electrochem. Soc., 140, pp 1713, 1993), the thickness of a crystal defect layer at the SOI layer was found to be about 200 nm. The defect layer is considered to be attributable to deformations and damages generated at the time of hydrogen ion implantation.
Such a defect layer can be eliminated if the amount of stock removed through touch polishing is increased to 200 nm or more. However, in this case, the uniformity of stock removal over the entire surface of a wafer deteriorates, resulting in an increased variation in the thickness of the SOI layer. Especially when the thickness of the SOI layer is small, the increased variation in the thickness causes greatly adverse effects on semiconductor devices, with the result that product value is lost.